Read-only memory cell arrangements having electrically writable and electrically erasable read-only memory cells using silicon technology, so-called flash EEPROMs, are required for many applications. These flash EEPROM arrangements retain the stored data even without a voltage supply.
In technical terms, these memory cells are mainly realized by an MOS transistor, which has, on the channel region, a first dielectric, a floating gate, a second dielectric and a control gate. If a charge is stored on the floating gate, then it influences the threshold voltage of the MOS transistor. In such a memory cell arrangement, the state "charge on the floating gate" is assigned to a first logic value and the state "no charge on the floating gate" is assigned to a second logic value. The information is written to the memory cells by means of a Fowler/Nordheim tunnelling current, by which electrons are injected onto the floating gate. The information is erased by a tunnelling current in the opposite direction through the first dielectric.
In memory cell arrangements of this type, the MOS transistors are constructed as planar MOS transistors and are arranged in a planar cell architecture. As a result, the theoretical minimum area requirement of a memory cell is 4F.sup.2, where F is the smallest structure size that can be produced with the respective technology. Flash EEPROM arrangements of this type are currently offered for volumes of data of at most 64 Mbits.
Larger volumes of data can currently be stored in a writable and erasable manner only in dynamic memory cell arrangements (DRAM) or on magnetic data media. A DRAM continually requires a voltage supply in order to retain the stored data. Magnetic data media, on the other hand, are based on mechanical systems with rotating storage media.
The invention is based on the problem of specifying an electrically writable and erasable read-only memory cell arrangement which can be produced with a smaller area requirement for each memory cell. It is furthermore intended to specify a method for the production of such a memory cell arrangement.